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icm7377b/7357b/7337b quad 12/10/8-bit voltage output dacs with serial interface and adjustable output gain rev. a8 icmic reserves the right to change the spec ifications without prior notice. 1 ic microsystems ic mic features ? 12/10/8-bit monotonic quad dac in 20 lead qsop package ? adjustable output gain ? wide output voltage swing ? 150 a per dac at 5v supply ? 100 a per dac at 3v supply ? on board reference ? serial interface with three-wire spi/qspi and microwire interface compatible ? serial data out for daisy-chaining ? 8 s full scale settling time application ? battery-powered applications ? industrial process control ? digital gain and offset adjustment overview the icm7377b, ICM7357B and icm7337b are quad 12- bit, 10-bit and 8-bit wide output voltage swing dac s respectively, with guaranteed monotonic behavior. t hese dacs are available in 20 lead qsop package. they include adjustable output gain for ease of use and flexibility. the reference output is available on a separate pin and can be used to drive external loads. the op erating supply range is 2.7v to 5.5v. the input interface is an easy to use three-wire sp i/qspi and microwire compatible interface. the dac has a double buffered digital input. and there is a seria l data output port to allow daisy-chaining applications. block diagram input and dac latch input control logic, registers and latches input and dac latch reference voa vob fba fbb sdi sck cs icm7377b/7357b/7337b dac b dac a input and dac latch input and dac latch dac d dac c voc vod fbc fbd sdo refcd refab + - + - + - + - clr refout
icm7377b/7357b/7337b quad 12/10/8-bit voltage output dacs with serial interface and adjustable output gain rev. a8 icmic reserves the right to change the spec ifications without prior notice. 2 ic microsystems ic mic package 20 lead qsop vdd 1 20 agnd fba 2 19 fbd voa 3 18 vod vob 4 17 voc fbb 5 16 fbc refab 6 15 refcd clr 7 14 n/c cs 8 13 refout sdi 9 12 sdo sck 10 11 dgnd top view pin description (20 lead qsop) pin name i/o description 1 vdd i supply voltage 2 fba i inverting input of the output amplifier dac a. output amplifier feedback input. 3 voa o dac a output voltage 4 vob o dac b output voltage 5 fbb i inverting input of the output amplifier dac b. output amplifier feedback input. 6 refab i reference voltage input for dac a and dac b 7 clr i active low clear input (cmos). resets all registe rs to zero. dac outputs go to 0 v 8 cs i active low chip select (cmos) 9 sdi i serial data input (cmos) 10 sck i serial clock input (cmos) 11 dgnd i digital ground 12 sdo o serial data output 13 refout o reference output 14 n/c - no connection 15 refcd i reference voltage input for dac c and da c d 16 fbc i inverting input of the output amplifier da c c. output amplifier feedback input. 17 voc o dac c output voltage 18 vod o dac d output voltage 19 fbd i inverting input of the output amplifier da c d. output amplifier feedback input. 20 agnd i analog ground
icm7377b/7357b/7337b quad 12/10/8-bit voltage output dacs with serial interface and adjustable output gain rev. a8 icmic reserves the right to change the spec ifications without prior notice. 3 ic microsystems ic mic absolute maximum rating symbol parameter value unit v dd supply voltage -0.3 to 7.0 v i in input current +/- 25.0 ma v in _ digital input voltage (sck, sdi, cs , clr ) -0.3 to 7.0 v v in _ ref reference input voltage -0.3 to 7.0 v t stg storage temperature -65 to +150 o c t sol soldering temperature 300 o c note : stress greater than those listed under absolute maxim um ratings may cause permanent damage to the device. t his is a stress rating only and functional operation of the device at these or any other conditions above those indicated in t he operational sections of this specification is not implied. exposure to absolute maximu m rating conditions for extended periods may affect reli ability. ordering information part operating temperature range package icm7377b -40 o c to 85 o c 20-pin qsop ICM7357B -40 o c to 85 o c 20-pin qsop icm7337b -40 o c to 85 o c 20-pin qsop dc electrical characteristics (v dd = 2.7v to 5.5v; v out unloaded; all specifications t min to t max unless otherwise noted) symbol parameter test conditions min typ max unit dc performance icm7377b n resolution 12 bits dnl differential nonlinearity (notes 1 & 3) 0.4 + 1.0 lsb inl integral nonlinearity (notes 1 & 3) 4.0 + 12.0 lsb ICM7357B n resolution 10 bits dnl differential nonlinearity (notes 1 & 3) 0.1 + 1.0 lsb inl integral nonlinearity (notes 1 & 3) 1.0 + 3.0 lsb icm7337b n resolution 8 bits dnl differential nonlinearity (notes 1 & 3) 0.05 + 1.0 lsb inl integral nonlinearity (notes 1 & 3) 0.25 + 0.75 lsb ge gain error + 0.5 % of fs oe offset error + 25 mv power requirements v dd supply voltage 2.7 5.5 v i dd supply current 0.6 1.5 ma
icm7377b/7357b/7337b quad 12/10/8-bit voltage output dacs with serial interface and adjustable output gain rev. a8 icmic reserves the right to change the spec ifications without prior notice. 4 ic microsystems ic mic symbol parameter test conditions min typ max unit output characteristics output voltage range (note 3) 0 v dd v vo sc short circuit current 60 150 ma r out amp output impedance at mid-scale (note 2) at 0-scale (note 2) 1.0 100 5.0 200 output line regulation v dd =2.7 to 5.5 v 0.4 3.0 mv/v logic inputs v ih digital input high (note 2) 2.4 v v il digital input low (note 2) 0.8 v digital input leakage 5 ? reference v refout reference output 1.2 1.25 1.3 v reference output line regulation v dd =2.7 to 5.5 v 0.8 4.0 mv/v ac electrical characteristics (v dd = 2.7v to 5.5v; v out unloaded; all specifications t min to t max unless otherwise noted) symbol parameter test conditions min typ max unit sr slew rate 2 v/s settling time 8 s mid-scale transition glitch energy 40 nv-s note 1: linearity is defined from code 64 to 4095 ( icm7377b) linearity is defined from code 16 to 1023 (icm7357 b) linearity is defined from code 4 to 255 (icm7337b) note 2: guaranteed by design; not tested in pro duction note 3: see applications information note 4: all digital inputs are either at gnd or v dd timing characteristics (v dd = 2.7v to 5.5v; all specifications t min to t max unless otherwise noted) symbol parameter test conditions min typ max unit t 1 sck cycle time (note 2) 30 ns t 2 data setup time (note 2) 10 ns t 3 data hold time (note 2) 10 ns t 4 sck falling edge to cs rising edge (note 2) 0 ns t 5 falling edge to sck rising edge cs (note 2) 15 ns t 6 pulse width cs (note 2) 20 ns
icm7377b/7357b/7337b quad 12/10/8-bit voltage output dacs with serial interface and adjustable output gain rev. a8 icmic reserves the right to change the spec ifications without prior notice. 5 ic microsystems ic mic figure 1. serial interface timing diagram t 1 t 2 t 3 t 4 t 5 t 6 c3 d0 sck cs sdi dac input word
icm7377b/7357b/7337b quad 12/10/8-bit voltage output dacs with serial interface and adjustable output gain rev. a8 icmic reserves the right to change the spec ifications without prior notice. 6 ic microsystems ic mic figure 2. serial interface operation diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sck sdi cs c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sdo c3 input word w -1 input word w 0 input word w 0 control word data word (update output) (enable sck)
icm7377b/7357b/7337b quad 12/10/8-bit voltage output dacs with serial interface and adjustable output gain rev. a8 icmic reserves the right to change the spec ifications without prior notice. 7 ic microsystems ic mic contents of input shift register icm7377b (12-bit dac) msb lsb c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 control word data word figure 3. contents of icm7377b input shift register ICM7357B (10-bit dac) msb lsb c3 c2 c1 c0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x control word data word x x figure 4. contents of ICM7357B input shift register icm7337b (8-bit dac) msb lsb c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 x x x x control word data word x x x x figure 5. contents of icm7337b input shift register c3 c2 c1 c0 data (d0 - d11) function 0 0 0 0 data load input latch dac a 0 0 0 1 data update dac a 0 0 1 0 data load input latch and update dac a 0 0 1 1 data load input latch dac b 0 1 0 0 data update dac b 0 1 0 1 data load input latch and update dac b 0 1 1 0 data load input latch dac c 0 1 1 1 data update dac c 1 0 0 0 data load input latch and update dac c 1 0 0 1 data load input latch dac d 1 0 1 0 data update dac d 1 0 1 1 data load input latch and update dac d 1 1 0 0 data load input latch all dacs 1 1 0 1 data update all dacs 1 1 1 0 data load input latch and update all dacs 1 1 1 1 x no operation table 1. serial interface input word
icm7377b/7357b/7337b quad 12/10/8-bit voltage output dacs with serial interface and adjustable output gain rev. a8 icmic reserves the right to change the spec ifications without prior notice. 8 ic microsystems ic mic detailed description the icm7377b is a 12-bit voltage output quad dac. t he ICM7357B is the 10-bit version of this family and t he icm7337b is the 8-bit version. this family of dacs employs a resistor string archi tecture guaranteeing monotonic behavior. there is a 1.25v onboard reference and an operating supply range of 2.7v to 5.5v. reference input there are two reference inputs that can be driven f rom ground to v dd ?1.5v. determine the output voltage using the following equation: v out = v ref x (d / (2 n )) where d is the numeric value of dac?s decimal input code, v ref is the reference voltage and n is number of bits, i.e. 12 for icm7377b, 10 for ICM7357B and 8 f or icm7337b. reference output the reference output is nominally 1.25v and is brou ght out to a separate pin and can be used to drive external loads. the outputs will nominally swing from 0 to 2.5v. output amplifier the quad dac has 4 output amplifiers with a wide ou tput swing. the actual swing of the output amplifiers wi ll be limited by offset error and gain error. see the app lications information section for a more detailed discussion. the 4 output amplifier?s inverting input of 4 dacs are available to the user, allowing force and sense cap ability for remote sensing and specific gain adjustment. th e unity gain can be provided by connecting the inverting in put to the output. the output amplifier can drive a load of 2.0 k to v dd or gnd in parallel with a 500 pf load capacitance. the output amplifier has a full-scale typical settl ing time of 8 s and it dissipates about 100 a with a 3v suppl y voltage. serial interface and input logic this quad dac family uses a standard 3-wire connect ion compatible with spi/qspi and microwire interfaces. data is loaded in 16-bit words which consist of 4 addres s and control bits (msbs) followed by 12 bits of data (se e table 1). the icm7357 has the last 2 lsbs as don?t care a nd the icm7337 has the last 4 lsbs as don?t care. the dac is double buffered with an input latch and a dac latch . serial data input sdi (serial data input) pin is the data input pin f or all dacs. data is clocked in on the rising edge of sck which has a schmitt trigger internally to allow for noise immunity on the sck pin. this specially eases the use for op to- coupled interfaces. the chip select pin which is the 8 th pin of 20 qsop package is active low. this pin must be low when da ta is being clocked into the part. after the 16 th clock pulse the chip select pin must be pulled high (level-triggere d) for the data to be transferred to an input bank of latc hes. this pin also disables the sck pin internally when pulle d high and the sck pin must be low before this pin is pull ed back low. as the chip select pin is pulled high the shif t register contents are transferred to a bank of 16 latches (s ee figure 2.). the 4 bit control word (c3~c0) is then decoded and the dac is updated or loaded depending on the control word (see table 1). the dac has a double-buffered input with an input l atch and a dac latch. the dac output will swing to its n ew value when data is loaded into the dac latch. the u ser has three options: loading only the input latch, up dating the dac with data previously loaded into the input latch or loading the input latch and updating the dac at the same time with a new code. serial data output sdo (serial data output) is the internal shift regi ster?s output. this pin can be used as the data output pin for daisy-chaining and data readback. and it is compati ble with spi/qspi and microwire interfaces. power-on reset there is a power-on reset on board that will clear the contents of all the latches to all 0s on power-up a nd the dac voltage output will go to ground. applications information power supply bypassing and layout considerations as in any precision circuit, careful consideration has to be given to layout of the supply and ground. the retur n path from the gnd to the supply ground should be short w ith low impedance. using a ground plane would be ideal. the supply should have some bypassing on it. a 10 f tantalum capacitor in parallel with a 0.1 f cerami c with a low esr can be used. ideally these would be placed as close as possible to the device. avoid crossing dig ital and analog signals, specially the reference, or running them close to each other. output swing limitations the ideal rail-to-rail dac would swing from gnd to v dd . however, offset and gain error limit this ability. figure 6 illustrates how a negative offset error will affect the output. the output will limit close to ground since this is single supply part, resulting in a dead-band area. as a la rger input is loaded into the dac the output will eventu ally rise above ground. this is why the linearity is specifie d for a starting code greater than zero. figure 7 illustrates how a gain error or positive o ffset error will affect the output when it is close to v dd . a positive gain error or positive offset will cause the output to be limited to the positive supply voltage resulting in a dead- band of codes close to full-scale.
icm7377b/7357b/7337b quad 12/10/8-bit voltage output dacs with serial interface and adjustable output gain rev. a8 icmic reserves the right to change the spec ifications without prior notice. 9 ic microsystems ic mic deadband negative offset f igure 6. effect of negative offset figure 7. effect of gain error and positive offset deadband positive offset offset and gain error v dd
icm7377b/7357b/7337b quad 12/10/8-bit voltage output dacs with serial interface and adjustable output gain rev. a8 icmic reserves the right to change the spec ifications without prior notice. 10 ic microsystems ic mic package information 20 qsop
icm7377b/7357b/7337b quad 12/10/8-bit voltage output dacs with serial interface and adjustable output gain rev. a8 icmic reserves the right to change the spec ifications without prior notice. 11 ic microsystems ic mic ordering information icm73x7b p g device 7 - icm7377b 5 - ICM7357B 3 - icm7337b g = rohs compliant lead - free packag e . blank = standard package. non lead-free. package q = 20-lead qsop

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